1. Field of the Disclosure
The present disclosure relates to a method of fabricating a semiconductor device, and more specifically to a method of forming a spacer patterning mask.
2. Description of the Related Art
Development of semiconductor process technology towards an increasingly smaller node poses various new challenges. One of the challenges in making the nodes smaller is presented by lithography. In lithography, many believe that double patterning technology will probably be the final solution for mass production and continued scale-down of the IC structure.
Currently, there are primarily three typical double patterning technologies: Litho-Etch-Litho-Etch (LELE) shown in FIG. 1A, Litho-Freeze-Litho-Etch (LFLE) shown in FIG. 1B, and spacer self-aligned double patterning (SADP) shown in FIG. 1C.
As shown in FIG. 1A, LELE entails a first litho step followed by a first etch step, a second litho step, and a second etch step. The precision level of the two litho steps is important for producing correct superimposition of layers. In other words, the alignment of a pattern exposed by the first litho step and a pattern exposed by the second litho step should be precise and accurate. Achieving the precise alignment with two lithography steps is challenging.
LFLE freezes a light-stop pattern and eliminates an etch step, but two high-precision lithography steps are still required to align the positions of the patterns.
SADP uses one critical etch step and thus avoids the double-litho challenge that is mentioned above. Moreover, the mask pattern formed by SADP comprises multiple etch steps and thus reduces critical dimension (CD) uniformity requirements in a single etch.
However, in the currently adopted SADP process, spacer deposition and etch process will cause a worse line width roughness (LWR) phenomena, for example, nonuniform line width and interval such as what is shown in FIG. 2, which will make a disadvantageous impact on the device performance.